1. Field of the Invention
This invention relates to a system and method for reducing LBIST manufacturing test time of integrated circuits.
2. Description of Background
Logic Built In Self Testing (LBIST) is relied upon to screen defects in particular AC or high-speed defects. Defects may include, for example, improper cleaning of level-to-level contact etching. To achieve test coverage, many setup configurations are used to achieve test coverage, for example, weight sets, array interface path selections, skewed versus unskewed scanning techniques, phase clocking sequences. For each instance, defect coverage is initially relatively excitingly high, but decreases with run time statistically as the self-generated patterns move in the “been-there/done-that” category. But occasionally a pattern is generated that provides unique defect coverage and fault grading identifies those patterns along with the corresponding pseudo-random pattern generator (PRPG) seed. Reloading and restarting LBIST with PRPG seeds that provide unique defect coverage adds to the manufacturing test time, but often this current approach of re-seeding PRPG does in fact reduce overall test time relative to having to extend the LBIST run-time. However, the reseeding overhead is still costly in terms of tester time because of the thousands and in some cases tens of thousands of LBIST reloads and restarts that is needed to cleanup the remaining though to detect defects.